| Gehäuse |
TSOP2
|
| Verpackung |
TRAY
|
| RoHS |
RoHS
|
| Spannungsversorgung |
3.3 V
|
| Betriebstemperatur |
0 C~+70 C
|
| Geschwindigkeit |
133 MHZ
|
| Standard Stückzahl |
|
| Abmessungen Karton |
|
| Number Of Words |
4M
|
| Bit Organization |
x16
|
| Density |
64M
|
| Package Material |
normal
|
| Interface |
LVTTL
|
| Hynix Memory |
HY
|
| No Of Banks |
4 banks
|
| Die Generation |
5th Gen.
|
| Power Consumption |
low power
|
| Shipping Method |
tray
|
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications r which require
low power consumption and extended temperature range. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.
