|Part No||128MX4 SD|
|Std. Pack Qty||540|
The EDS5104AB is a 512M bits SDRAM organized as
33,554,432 words × 4 bits × 4 banks. All inputs and outputs
are referred to the rising edge of the clock input.
It is packaged in standard 54pin plastic TSOP (II).
• 3.3V power supply
• Clock frequency: 166MHz/133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• 4 banks can operate simultaneously and independently
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
- Auto refresh
- Self refresh
|Part No||64MX8 NAND SLC|
|Outpack||TAPE ON REEL|
|Std. Pack Qty||2000|
Offered in 64Mx8bits, the K9F1208U0C is 512Mbit with spare 16Mbit capacity. The device is offered in 3.3V Vcc.
Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation
can be performed in typical 200µs on the 528-bytes and an erase operation can be performed in typical 2ms on
a 16K-bytes block. Data in the page can be read out at 42ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output as well as command input.
The on-chip write control automates all program and erase functions including pulse repetition, where required,
and internal verification and margining of data.
Even the write-intensive systems can take advantage of the K9F1208X0C′s extended reliability of 100K
program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
• Package :
K9F1208U0C-JIB0: Pb-Free Package
63-Ball FBGA (8.5 x 13 x 1.2mmt)
• Voltage Suppl :
3.3V Device (K9F1208U0C) : 2.7V ~ 3.6V
• Organization :
Memory Cell Array : (64M + 2M) x 8bits
Data Register : (512 + 16) x 8bits
About 100 k of this parts are after 3 years ( D/C 2011 ) new packed and sealed.
This parts are in new "static shield moisture bags" and without Box.
|Part No||32MX16 NAND|
|Std. Pack Qty||1600|
OneNAND™‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device
includes control logic, a NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot
code buffering (BootRAM) and 4KB for data buffering (DataRAM), split between 2 independent buffers. It has a x16
Host Interface and a random access time speed of ~76ns.
The device operates up to a maximum host-driven clock frequency of 66MHz for synchronous reads at Vcc(or Vccq.
Refer to chapter 4.2) with minimum 6-clock latency. Below 40MHz it is accessible with minimum 3-clock latency.
Appropriate wait cycles are determined by programmable read latency.
OneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector
counter register. The device includes one block-sized OTP (One Time Programmable) area and user-controlled 1st block
OTP(Block 0) that can be used to increase system security or to provide identification capabilities.
• Supply Voltage: 3.3V(2.7V to 3.6V)
• Host Interface: 16 bit
• 5KB Internal BufferRAM: 1KB BootRAM, 4KB DataRAM
Synchronous Burst Read
- Up to 66MHz clock frequency
- Linear Burst 4-, 8-, 16-, 32-words with wrap around
- Continuous 1K words Sequential Burst
Asynchronous Random Read
- 76ns access time
Asynchronous Random Write
Latency 3,4(Default),5,6 and 7.
1~40MHz : Latency 3 available
1~66MHz : Latency 4,5,6 and 7 available
Up to 4 sectors using Sector Count Register
Cold/Warm/Hot/NAND Flash Core Reset
up to 64 Blocks
- Standby current : 35uA
- Synchronous Burst Read current(66MHz) : 25mA
- Load current : 30mA
- Program current : 28mA
- Erase current : 23mA
- Multi Block Erase current : 23mA
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Package : 67FBGA(LF)
|Part No||16MX32 MSDRAM|
|Std. Pack Qty||1120|
The K4M51323PI is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 32 bits, fabricated with SAMSUNG’s
high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful
for a variety of high bandwidth and high performance memory system applications.
• VDD/VDDQ = 1.8V/1.8V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Extended Temperature Operation (-25°C ~ 85°C).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 90Balls FBGA( -SXXX -Pb, -DXXX -Pb Free).
|Part No||8MX16 MDDR1|
|Outpack||TAPE ON REEL|
|Std. Pack Qty||2000|
|Temperature||-25°C ~ 70°C|
|Speed||C3: 133MHZ, CL 3|
8M x16 Mobile-DDR SDRAM
• 1.8V power supply, 1.8V I/O power
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• Deep Power Down Mode
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• LDM/UDM for write masking only.
• Auto refresh duty cycle
- 15.6us for -25°C to 85°C