| 脚位/封装 |
TSOP-48
|
| 外包裝 |
TRAY
|
| 無鉛/環保 |
含鉛
|
| 電壓(伏) |
2.7V~3.6V
|
| 溫度規格 |
-40 C~+85 C
|
| 速度 |
90 NS
|
| 標準包裝數量 |
576
|
| 標準外箱 |
|
SUMMARY DESCRIPTION
The M28W320C is a 32 Mbit (2 Mbit x 16) non-volatile Flash memory that can be erased electrically
at the block level and programmed in-system on a
Word-by-Word basis. These operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. VDDQ allows to drive the I/O pin down to
1.65V. An optional 12V VPP power supply is provided to speed up customer programming.
The device features an asymmetrical blocked architecture. The M28W320C has an array of 71
blocks: 8 Parameter Blocks of 4 KWord and 63
Main Blocks of 32 KWord. M28W320CT has the
Parameter Blocks at the top of the memory address space while the M28W320CB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 6, Block Addresses.
The M28W320C features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase.
When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at Power
Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divided into two 64 bit segments, the first one contains
a unique device number written by ST, while the
second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block,
parameter block 0, can be permanently protected
by the user. Figure 7, shows the Security Block
and Protection Register Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
