| 脚位/封装 |
TSOP2
|
| 外包装 |
TRAY
|
| 无铅/环保 |
含铅
|
| 电压(伏) |
3.3 V
|
| 温度规格 |
0 C~+70 C
|
| 速度 |
133 MHZ
|
| 标准包装数量 |
|
| 标准外箱 |
|
| Number Of Words |
8M
|
| Bit Organization |
x16
|
| Density |
128M
|
| Package Material |
normal
|
| Interface |
LVTTL
|
| Hynix Memory |
HY
|
| No Of Banks |
4 banks
|
| Die Generation |
4th Gen.
|
| Power Consumption |
normal power
|
| Shipping Method |
tray
|
DESCRIPTION
The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V281620HC(L/S)T is organized as 4banks of 2,097,152x16
HY57V281620HC(L/S)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.
